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1 ? fn8243.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2005. all rights reserved all other trademarks mentioned are the property of their respective owners. isl96017 128-tap dcp, 16kbit eeprom, and i 2 c serial interface this device integrates a 128-tap digitally controlled potentiometer, 16kbit of eeprom, and a 2-wire i 2 c serial interface. the device is powered by a single 3.3v supply. the potentiometer is available with total resistance of either 10k ? or 50k ? . the memory is organized in 128 pages of 16 bytes each, to reduce total programming time. all programming signals are generated on-chip. the potentiometer is implemen ted with a combination of cmos switches and resistor elements. the position of the wiper can be stored in non-volatile memory and then be recalled upon a subsequent power-up. the three terminals of the potentiometer are availabl e for use as either a variable resistor or a resistor divider. pinout isl96017 (8 ld tdfn) top view features ? integrated digitally controlled potentiometer - 128-tap positions -10k ?, 50k ? total resistance - monotonic over temperature - non-volatile wiper position storage - 0 to vdd terminal voltage ?i 2 c serial interface ? 16kbit eeprom - 50 years retention @ 55c - 1,000,000 cycles endurance ? single 3.3 0.3v supply ? 3mm x 3mm thin dfn package ? 0.8mm max thickness, 0.65mm pitch ? pb-free plus anneal available (rohs compliant) rh rw rl vdd wp scl sda gnd 2 3 4 1 7 6 5 8 ordering information part number part marking r total (k ? ) temp. range (c) package pkg. dwg. # isl96017wirt8z* (note) 96017wiz 10 -40 to 85 8 ld 3x3 tdfn (pb-free) l8.3x3a ISL96017UIRT8Z* (note) 96017uiz 50 -40 to 85 8 ld 3x3 tdfn (pb-free) l8.3x3a *add "-tk" suffix for 1000 units tape and reel. note: intersil pb-free plus anneal products employ special pb-free material sets; mo lding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet april 17, 2006
2 fn8243.1 april 17, 2006 block diagram sda scl wp power-up, interface, and control logic 16kbit eeprom rh rl rw pin descriptions pin symbol description 1 rh ?high? terminal of the dcp 2 rw ?wiper? terminal of the dcp 3 rl ?low? terminal of the dcp 4 vdd power supply 5 gnd ground 6 sda open drain serial interface data input/output 7 scl open drain serial interface clock input 8wp hardware write protection pin. active low. prevents any ?write? operation to the device. isl96017
3 fn8243.1 april 17, 2006 absolute maximum rati ngs thermal information storage temperature: . . . . . . . . . . . . . . . . . . . . . . . .-65c to 150c note: all voltages with respect to gnd voltage at scl, sda, wp : . . . . . . . . . . . . . . . . . . . . . -0.3v to 4v voltage at rh, rw, rl: . . . . . . . . . . . . . . . . . . . . . . . gnd to vdd vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 4v lead temperature (soldering, 10s): . . . . . . . . . . . . . . . . . . . . 300c wiper current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma esd (mil-std-883b, method 3014) . . . . . . . . . . . . . . . . . . .>2000v esd (machine model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>150v thermal resistance (typical, note 1) ja 8 ld tdfn package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90(c/w) moisture sensitivity (see technical brief tb363). . . . . . . . . .level 2 maximum junction temperature (plastic package). . . . . . . . . .150c recommended operating conditions ambient temperature . . . . . . . . . . . . . . . . . . . . . . . . . -40c to 85c vdd voltage for dcp operation . . . . . . . . . . . . . . . . . . 3.0v to 3.6v wiper current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3ma to 3ma power rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mw caution: stresses above those listed under ?absolute maximum rating s? may cause permanent damage to the device. this is a stres s rating only; the functional operation of the device, at these or any other conditions above those listed in the op erational sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: 1. ja is measured in free air with the component mounted on a high effe ctive thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379 for details. electrical specifications over recommended operating conditions unless otherwi se stated. all voltages with respect to gnd. symbol parameter test conditions min typ (note 1) max unit iccdsby standby current at vdd serial interface in standby 10 a iccdrd read current at vdd reading with 400khz at scl 1 ma iccdwr write current at vdd writing to eeprom 5 ma i lkgdig leakage current at pins sda, scl, and wp pin voltage from gnd to vdd -10 10 a i lkgdcp leakage current at rh, rw, rl pin voltage from gnd to vdd -1 1 a vddramp vdd power-up ramp rate 0.2 v/ms t dcp (note 13) dcp wiper response time scl falling edge of last bit of dcp data byte to wiper change 1.5 s t d power-up delay vdd above 2.6v, to dcp initial value register recall completed, and i 2 c interface in standby state 3ms ch/cw/cl (note 13) rh, rw, rl pin capacitance 10 pf r to t a l total resistance w and u versions, respectively. t a =25c. measured between r h and r l pins. 10, 50 k ? r to ta l tolerance t a = 25c. measured between r h and r l pins. -20 20 % r wiper wiper resistance v dd = 3.3v @ 25c. wiper current = v dd /r to ta l 100 300 ? dcp resolution 7bits dcp in voltage divider mode (0v at rl, vcc at rh; measured at rw unloaded) fserror (note 2, 3) full-scale error u option -2 -1 0 lsb w option -5 -1 0 lsb zserror (note 2, 4) zero-scale error u option 0 1 2 lsb w option 0 1 5 lsb tc v (note 7, 13) ratiometric temperature coefficient dcp register between 10 hex and 6f hex 4 ppm/c dnl (note 2, 5) differential non-linearity monotonic over all tap positions -0.75 0.75 lsb inl (note 2, 6) integral non-linearity -1 1 lsb isl96017
4 fn8243.1 april 17, 2006 dcp in resistor mode (measurements between rh and rw with rl not connected) r 127 (note 8) resistance offset. u version - dcp register set to 7f hex. measured between r h and r w pins. 00.52mi w version - dcp register set to 7f hex. measured between r h and r w pins. 15mi tc r (note 11,13) resistance temperature coefficient 100 ppm/c rdnl (note 8,9) resistance differential non- linearity -0.75 0.75 mi (note 1) rinl (note 8,10) resistance integral non-linearity -1 1 mi (note 1) eeprom specs eeprom endurance 1,000,000 cycles eeprom retention at 55c 50 years t wc (note 12) non-volatile write cycle time 6 12 ms serial interface specs v il wp , sda, and scl input buffer low voltage -0.3 0.3* vdd v v ih wp , sda and scl input buffer high voltage 0.7* vdd vdd +0.3 v hysteresis sda and scl input buffer hysteresis 0.05* vdd v v ol sda output buffer low voltage, sinking 4ma 00.4v cpin wp , sda, and scl pin capacitance 10 pf f scl scl frequency 400 khz t in pulse width suppression time at sda and scl inputs. any pulse narrower than the max spec is suppressed 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing 30% of vdd, until sda exits the 30% to 70% of vdd window 900 ns t buf time the bus must be free before the start of a new transmission sda crossing 70% of vcc during a stop condition, to sda crossing 70% of vdd during the following start condition 1300 ns t low clock low time measured at the 30% of vdd crossing 1300 ns t high clock high time measured at the 70% of vdd crossing 600 ns t su:sta start condition setup time scl rising edge to sda falling edge. both crossing 70% of vdd 600 ns t hd:sta start condition hold time from sda falling edge crossing 30% of vdd to scl falling edge crossing 70% of vdd 600 ns t su:dat input data setup time from sda exiting the 30% to 70% of vdd window, to scl rising edge crossing 30% of vdd 100 ns t hd:dat input data hold time from scl rising edge crossing 70% of vdd to sda entering the 30% to 70% of vdd window 0ns t su:sto stop condition setup time from scl ri sing edge crossing 70% of vcc, to sda rising edge crossing 30% of vdd 600 ns electrical specifications over recommended operating conditions unless otherwi se stated. all voltages with respect to gnd. (continued) symbol parameter test conditions min typ (note 1) max unit isl96017
5 fn8243.1 april 17, 2006 i 2 c timing diagram t hd:sto stop condition hold time from sda rising edge to scl falling edge. both crossing 70% of vdd 600 ns t dh output data hold time from scl falling edge crossing 30% of vdd, until sda enters the 30% to 70% of vdd window 0ns t r sda and scl rise time from 30% to 70% of vdd 20+ 0.1*cb 250 ns t f sda and scl fall time from 70% to 30% of vdd 20+ 0.1*cb 250 ns cb capacitive loading of sda or scl total on-chip and off-chip 10 400 pf rpu sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f for cb = 400pf, max is about 2~2.5k ? for cb = 40pf, max is about 15~20k ? 1k ? t su:wp wp setup time before start condition 600 ns t hd:wp wp hold time after stop condition 600 ns notes: 2. typical values are for t a = 25c and v dd = 3.3v. 3. lsb = (v(rw) 127 ? v(rw) 0 )/127. v(rw) 127 and v(rw) 0 are the voltage at pin rw for the dcp register set to 7f hex and 00 hex respectively. 4. fserror = (v(rw) 127 ? vdd)/lsb 5. zserror = v(rw) 0 /lsb 6. dnl = [(v(rw) i ? v(rw) i-1 )/lsb] ? 1, for i from 1 to 127. i is the dcp register setting. 7. inl = [v(rw) i ? i * lsb ? v(rw) 0 ]/lsb, for i = 1 to 127. 8. for i = 16 to 111, and t = -40c to 85c 9. mi = (r 0 ? r 127 )/127. mi is minimum increment. r 0 and r 127 are the resistances between rh and rw with the dcp register set to 00 hex and 7f hex, respectively. 10. rdnl = (r i ? r i-1 )/mi ? 1, for i from 1 to 111. i is the dcp register setting. 11. rinl = [r i ? (mi * i) ? r 127 ]/mi, for i from 1 to 111. 12. ; for i = 1 to 111, and t = -40c to 85c 13. t wc is the minimum cycle time to be allow ed for any non-volatile write by the user, unless acknowledge polling is used. it is the time from a valid stop condition at the end of a write sequence of a i 2 c serial interface write operation, to the end of the self-timed internal non-volatile write cycle. 14. parameter is not 100% tested. electrical specifications over recommended operating conditions unless otherwi se stated. all voltages with respect to gnd. (continued) symbol parameter test conditions min typ (note 1) max unit tc v max v rw () i () min v rw () i () ? [] max v rw () i () min v rw () i () + () 2 ? ---------------------------------------------------------------------------------------------- - 10 6 125 c ----------------- = tc r max ri () min ri () ? [] max ri () min ri () + [] 2 ? --------------------------------------------------------------- - 110 6 125 c ------------------ - = t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r isl96017
6 fn8243.1 april 17, 2006 typical performance curves figure 1. wiper resistance vs tap position for 10k ? (w) figure 2. dnl vs tap position for 10k ? (w) figure 3. inl vs tap position for 10k ? (w) figure 4. rdnl vs tap position for 10k ? (w) figure 5. rinl vs tap position for 10k ? (w) 0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140 tap position (decimal) wiper resistance ( ? ) v dd = 3.6v v dd = 3.0v t = 25c -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0 20 40 60 80 100 120 140 tap position (decimal) dnl (lsb) v dd = 3.0v v dd = 3.6v t = 25c -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 20 40 60 80 100 120 140 tap position (decimal) inl (lsb) v dd = 3.6v v dd = 3.0v t = 25c -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 20 40 60 80 100 120 140 tap position (decimal) rdnl (lsb) t = 25c v dd = 3.6v v dd = 3.0v -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0 20 40 60 80 100 120 140 tap position (decimal) rinl (lsb) t = 25c v dd = 3.6v v dd = 3.0v isl96017
7 fn8243.1 april 17, 2006 principles of operation this device combines a dcp, 16kbit non-volatile memory, and an i 2 c serial interface providing direct communication between a host and the dcp and memory. dcp description the dcp has 10k ? or 50k ? nominal total resistance and 128 taps. it is implemented with a combination of resistor elements and cmos switches. the physical ends of the dcp, the rh and rl pins, are equivalent to the fixed terminals of a mechanical potentiometer. the rw pin is connected to intermediate nodes, and it is equivalent to the wiper terminal of a mechanical potentiometer. the position of the wiper terminal within the dcp is controlled by a 7-bit volatile dcp register. when the dcp register contains all zeroes (00 hex, or ?r 0 ?), its wiper terminal, rw, is closest to its rl terminal. when the dcp register contains all ones (7f hex, or ?r 127 ?), its wiper terminal is closest to its rh terminal. as the value of the dcp register increases from all zeroes to all ones, the wiper moves monotonically from the position closest to rl to the closest to rh. therefore, the resistance between rh and rw decreases monotonically from r 0 to r 127 , while the resistance between rw and rl increases monotonically from r 127 to r 0 . while the device is being powered up, the dcp register is reset to 40 hex (64 decimal). soon after the power supply voltage becomes large enough for reliable non-volatile memory reading, the device reads the value stored on the non-volatile initial value register (ivr) and loads it into the dcp register. memory description this device contains 2048 non-volatile bytes organized in 128 pages of 16 bytes each. this allows writing 16 bytes on a single i 2 c interface operation, followed by a single internal non-volatile write cycle. the memory is accessed by i 2 c interface operations with addresses 000 hex through 7ff hex. bytes at addresses 000 hex through 7fb hex are available to the user as general purpose memory. the byte at address 7ff hex, ivr, contains the initial value loaded at power-up into the volatile dcp register. the byte at address 7fe hex controls the access to the dcp byte (see ?access to dcp register and ivr?). bytes at addresses 7fc hex and 7fd hex, are reserved, which means that they should not be written, and their value should be ignored if they are read. (see table 1). access to dcp register and ivr the volatile dcp register and the non-volatile (ivr) can be read or written directly using the i 2 c serial interface, with address byte 07ff hex. the msb of the byte at address 7fe hex is called ?onlyvolatile? and controls the access to the dcp register and ivr. this bit is volatile and it?s reset to ?0? at power up. the data byte read from memory address 7ff hex, is from the dcp register when the ?onlyvolatile? bit is ?1?, and from the ivr when this bit is ?0?. the data byte of a write operation to memory address 7ff hex is written only to the dcp register when the ?onlyvolatile? bit is ?1?, and it?s written to both the dcp register and the ivr when this bit is ?0?. when writing to the ?onlyvolat ile? bit at address 7fe hex, the seven lsbs of the data byte must be all zeros. writing to address 7fe hex and 7ff hex can be done in two write operations, or one write operation with two data bytes. see next sections for interface protocol description. table 1. isl96017 memory map address data bits function 7ffh 0 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ivr, dcp 7fehov0000000 access control 7fdh reserved 7fch reserved 7fbh d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 general purpose memory 000h note: ov = ?only volatile?. all other bits in register 7feh must be 0. isl96017
8 fn8243.1 april 17, 2006 i 2 c serial interface this device supports a bidire ctional bus oriented protocol. the protocol defines any devic e that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and receive operatio ns. therefore, this device operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of each byte of data first. protocol conventions data states on the sda line can change only during scl low periods. sda state cha nges during scl high are reserved for indicating start and stop conditions (see figure 6). on power up, the sda pin is in the input mode. all i 2 c interface operations must begin with a start condition, which is a high to low transition of sda while scl is high. the device continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 6). a start condition is ignored during the power up sequence and during internal non-volatile write cycles. all i 2 c interface operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 6). a stop condition at the end of a read operation, or at the end of a write oper ation to volatile bytes only places the device in its standby mode. a stop condition during a write operation to a non -volatile byte, initiates an internal non-volatile write cycl e. the device enters its standby state when the internal non-volatile write cycle is completed. an ack, acknowledge, is a software convention used to indicate a successful data transfer. the transmitting device, either master or slave, releases the sda bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data (see figure 7). this device responds with an ack after recognition of a start condition followed by a vali d identification byte, and once again after successful receipt of the address byte. this device also responds with an ack after receiving each data byte of a write operation. the master must respond with an ack after receiving each data byte of a read operation except the last one. a valid identification byte contains 1010 as the four msbs. the following three bits are the msbs of the memory address to be accessed. the lsb of the identification byte is the read/write bit. its value is ?1? for a read operation, and ?0? for a write operation (see table 2). the complete memory address location to be accessed is a 11-bit word, since the memory has 2048 bytes. the eight lsbs are in the address byte. table 2. identification byte format 1010a10a9a8r/wb msb lsb scl sda start stop scl sda data stable data change data stable figure 6. valid data changes, start and stop conditions isl96017
9 fn8243.1 april 17, 2006 write operation a write operation requires a start condition, followed by a valid identification byte, a valid address byte, one or more data bytes, and a stop condition (see figure 8). after each of the bytes, this device res ponds with an ack. at this time, if the operation is only writing to volatile registers, then the device enters its standby state. if one or more data bytes are to be written to non-volatile memory, the device begins its internal write cycl e to non-vola tile memory. during this cycle, the device ignores transitions at the sda and scl pins, and the sda output is at a high impedance state. when the internal non-volatile writ e cycle is completed, the device enters its standby state. the memory is organized as 128 pages of 16 bytes each. this allows writing 16 bytes on a single i 2 c interface operation, followed by a single internal non-volatile write cycle. the addresses of bytes within a page share the same eight msbs, and differ on the four lsbs. for example, the first page is located at addresses 0 hex through f hex, the second page is located at addresses 10 hex through 1f hex, etc. a write operation with more than one data byte sends the first data byte to the memory address indicated by the three address bits of the identification byte plus the eight bits of the address byte, the second data byte to the following address, etc. a single write operation has to stay within a page. if the address byte corresponds to the lowest address of a page, then the write operation can have anywhere from 1 to 16 data bytes. if the address byte corresponds to the highest address of a page, then only one byte can be written with that write operation. see ?access to dcp register and ivr? for additional information. data protection the wp pin has to be at logic high to perform any write operation to the device. when wp is active (low) the device ignores data bytes of a write operation, does not respond to them with ack, and instead, goes to its standby state waiting for a new start condition. a valid identification byte, addr ess byte, and total number of scl pulses act as a protecti on of both volatile and non- volatile registers. during a write sequence, data bytes are loaded into an internal shift register as they are received. if the address bits in the identification by te plus the bits in the address byte are all ones, the data byte is trans ferred to the dcp register at the falling edge of the scl pulse that loads the last bit (lsb) of the data byte. the stop condition acts as a protection of non-volatile memory. non-volatile internal write cycles are started by stop conditions. read operation a read operation consist of a three byte instruction followed by one or more data bytes (see figure 9). the master initiates the operation issuing the following sequence: a start, the identification byte with the r/w bit set to ?0?, an address byte which contains the lsbs of the memory address, a second start, and a second identification byte with the same address bits but with the r/w bit set to ?1?. after each of the three bytes, this device responds with an ack. then this device transmit s data bytes as long as the master responds with an ack during the scl cycle following the eighth bit of each byte. the master terminates the read operation (issuing a stop condit ion) following the last bit of the last data byte. the data bytes are from the memory location indicated by an internal pointer. this pointer initial value is determined by the address bits in the identification byte plus the bits in the address byte in the read operation instruction, and increments by one during transmission of each data byte. sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance high impedance figure 7. acknowledge response from receiver isl96017
10 fn8243.1 april 17, 2006 applications information the typical application diagram is shown on figure 10. for proper operation adding 0.1f decoupling ceramic capacitor to vdd is recommended . the capacitor value may vary based on expected noise frequency of the design. signals from the master signals from the slave signal at sda s t a r t slave address address byte a c k a c k first data byte to write s t o p a c k a c k last data byte to write write figure 8. write sequence 10 10 0 signals from the master signals from the slave signal at sda s t a r t slave address with r/wb=0 address byte a c k a c k 0 s t o p a c k 1 slave address with r/wb=1 a c k s t a r t last read data byte first read data byte a c k figure 9. read sequence 1010 read a c k vdd=3.3v vdd=3.3v vdd=3.3v vcc r1 r2 rpu 0.1uf isl96017 scl sda rh rw rl 0.1uf wp rpu vout figure 10. typical application diagram for implementing adjustable voltage referance isl96017
11 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8243.1 april 17, 2006 isl96017 thin dual flat no-lea d plastic package (tdfn) // nx (b) section "c-c" 5 (a1) bottom view a 6 area index c c 0.10 0.08 side view 0.15 2x e a b c 0.15 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a m c n-1 12 plane seating c a a3 nx b d2/2 nx k for even terminal/side e c l terminal tip l1 10 l l8.3x3a 8 lead thin dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.70 0.75 0.80 - a1 - 0.02 0.05 - a3 0.20 ref - b 0.25 0.30 0.35 5, 8 d 3.00 bsc - d2 2.20 2.30 2.40 7, 8, 9 e 3.00 bsc - e2 1.40 1.50 1.60 7, 8, 9 e 0.65 bsc - k0.25 - - - l 0.20 0.30 0.40 8 n82 nd 4 3 rev. 3 11/04 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. compliant to jedec mo-weec-2 except for the ?l? min dimension.

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